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8566 is not the same

Look no further than http://segher.ircgeeks.net/vic-ii/ :-)

The 8565-blocks.{jpg,xcf} shows all the pads, and names the functional
blocks. The 8565R2.xcf is my Gimp file where I labeled pretty much
every single signal on the chip.

There are five (octagonal, smaller) pads to the right. Those are four
color output bits (0 is black, 1 is white, 2 is red, 15 is light gray,
etc.), and a frame signal. I believe those are test pads.

The pad on the middle left is to connect the back bias generator to the
substrate.

The 8566 is a different die. It has some registers that are physically
not there on the 8565.

Cool, I used to have one of
Nice work :) Saves me a lot
You're welcome.

You're welcome.

Yes, # means not. It is the same as an overbar over the symbol. Some people write # after the symbol
instead, or write n or n_ before it. I like # because it is very visual, and I can actually type it :-) # on a pad
is best thought of as low active. like #IRQ is pulled low to trigger an interrupt, or R/#W means high for
read, low for write.

If you decap a chip, those pads might be exposed through overglass holes. I don't know.

I have never seen 8566 (VIC IIe) or 6566 (original VIC II, used in the MAX machine) die photographs.
The 8566 should have some extra circuitry, it's not obvious how that will fit in; probably it is all just
tucked away to a side ;-)

The 8565 (this chip) is a lot like the older 6569. The analogue portions (top right corner) have
different sizing; the RAS/CAS things are different, those depend on delays other than those
given by the clocks; back bias gen is different. That is about it.

In the oldest revisions of the 6569 there was a bug with the light pen (LP) interface, it had the
timing wrong. Supposedly old 6567 (NTSC version) dies had only five levels of luminosity,
not nine. Differences between the different region dies are (almost?) exclusively the X and Y
match ROMs.

The 6566 was first, and it didn't drive dynamic RAM, just static RAM. It had fourteen address
pins, not multiplexed, and no RAS and CAS. It should look nicer since the DRAM features
are rather tucked on. As said, the RAS/CAS do not really fit in with designed timing signals
on the chip (they time themselves, big delay chains etc.); and there is all this weird address
muxing (top left of the chip).

You see, the DRAM of the time had the address fed to them in two phases. First you had
RAS, "row address select", which selects one out of 128 or 256 rows; and then CAS, column
address select, which picks one of the 128 or 256 columns out of that row, and inputs/outputs
that bit (yes, bit, you have 8 chips in parallel to make a byte-wise system).

The VIC can handle either 128 or 256, with a small change to its metal layer. If you look at
the A11 pad, there are two biggish strips of polysilicon to the right of them, under the ground
ring. You see one connects to ground, and the other to 5V; the contacts are there for them
to be flipped around. The signals from there (I think I called them sa7, sa8; "select 8-bit
address") go to muxes, selecting the "high" address half; and then to muxes selecting high
or low. That is all in the top-left corner, above the clock drivers.

DRAM also needs periodic refresh: each row needs to be accessed periodically. That is
done by doing five accesses ever scan line, with a counter that just counts up. If you look
really carefully you'll see that it only counts seven bits, not eight; most chips only need to
have seven bits refresh though (old DRAM chips only *had* seven bits for the rows, many
refresh circuits only did seven, DRAM manufacturers wanted their new bigger chips to
work on those as well, those chips refresh two rows at once).

I can probably go on, If you have any questions... But first look at the chip :-)

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