Greetings all,
 
I just watched Jeri JeriEllsworth's video on Homebrew NMOS Transistor Step by Step
 
http://www.youtube.com/watch?v=w_znRopGtbE
 
(If you're not familiar with her (not you Bill :)),  she has photos of her "chip lab" on flickr:
http://www.flickr.com/photos/jeriellsworth/2835459827/
 
And videos on vimeo
How .. if at all, do the layers she describes correspond to the layers on
the visual6502 simulation ?
http://visual6502.org/JSSim/expert.html
 
Mike
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Jeri's Video :
 
- etch gate area
4 - intermediate oxide layer & drive In (oxide layer covers source & drain regsions)
- etch phosporosilica from drain, source
3 - phosporosilica film (predeposition) high concentration of phosporus into wafer
- etch source and drain (active layer) (back down to p-type)
2 = 5,000 angstrom oxide
1- p type wafer
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Simulator :
 
 
diffusion
grounded diffusion
powered diffusion
polysilicon
metal
protection